I scheduled next vector TG meeting tomorrow in usual slot with usual zoom link on TG Google calendar. I hope to push out updated spec sometime before then, Krste

I was going to restart the vector TG meetings next week (Jan 29), and have a goal of having most pending updates added to the spec a few days before then. Krste

I see it on riscv-v-spec commit: 0e8cdeb26bb98de2b1089d79a681af2c5a65e712 vmv.x.s rd, vs2 # x[rd] = vs2[0] (rs1=0) vmv.x.s belong to VWXUNARY0 and OPMVV But OPMVV has only vs1 no rs1, see : funct6 | v

I don’t see Vector Extension meetings on the calendar. Is the group meeting? Bill Bill Huffman Distinguished Engineer T: 408.944.7613

Agenda is hopefully clearing up any remaining major issues before 1.0 draft can go out, Krste

Date: 2020/12/04 Task Group: Vector Extension Chair: Krste Asanovic Co-Chair: Roger Espasa Number of Attendees: ~12 Current issues on github: https://github.com/riscv/riscv-v-spec Note: No meeting wee

Hi，David Can we see the git of your work? My code has not been upload to git, and I will show it in the mail. Does this mean the 32 vector registers are not enough, or that the number of elements for

Hi，all Recently, I optimized the kernel of GEMM for int8 data. I found that there was no good solution to do in by the use of the present vector ISA. The mainly difficult I meet is: The accumulator is

Next meeting today in usual time slot as on calendar, Krste Date: 2020/11/20 Task Group: Vector Extension Chair: Krste Asanovic Co-Chair: Roger Espasa Number of Attendees: ~17 Current issues on github

That is exactly what I want. Thanks Mark. Weiwei 发件人: tech-vector-ext@... <tech-vector-ext@...> 代表 mark 发送时间: 2020年11月25日 23:13 收件人: Wang Weiwei <Weiwei.Wang@...> 抄送: vector <tech-vector-ext@...> 主题:

Hi Krste and Andrew, What is the rough plan for rvv v1.0 release? I searched vector-ext mailing list but can’t find the info I want. Thanks Weiwei

I think we'll be spending a chunk of time on mask layout and implementation issues. See you then, Krste

This is issue #601. It was pointed out that *e7 (estimate to 7 bits) suffix on mnemonic is easily confused with e32 (element size 32) on other mnemonics. This is probably one we can handle on email th

Date: 2020/11/13 Task Group: Vector Extension Chair: Krste Asanovic Co-Chair: Roger Espasa Number of Attendees: ~22 Current issues on github: https://github.com/riscv/riscv-v-spec Issues discussed: #

In support of Open Source Software and publicly released modeling schemes, does the Vector Task Group have a recommendation for arithmetic reference? The published ISSs can provide checking results fr

Also, reminder we'll be meeting tomorrow (Friday Nov 13) as per calendar entry (7 hours from now), Krste Date: 2020/11/06 Task Group: Vector Extension Chair: Krste Asanovic Co-Chair: Roger Espasa Numb

Also on github as issue #595 In our earlier TG discussion in 9/18 meeting, we were in favor of allowing vector strided load instructions with rs1=x0 to perform fewer memory accesses than the number of

I've been thinking through the cases where a wide implementation that wants "slices" could have to introduce a hiccup to rearrange bytes because of an EEW change (since SLEN is gone). The ones I know

We'll meet per the calendar entry. Agenda is to go over any remaining unsettled open issues, Krste

Thanks Tim, I think that sums it up nicely. I just wanted to put a pointer out to the original post that I made on isa-dev regarding opcode sharing / management: https://groups.google.com/a/groups.ris