Date   
Whole Register Loads and Stores 14 messages By Bill Huffman ·
Vector TG meeting minutes for 2020/6/19 By Krste Asanovic ·
Minutes of 2020/6/12 vector TG meeting By Krste Asanovic ·
Fault-Only-First Indexed Loads Instructions 4 messages By lidawei14@... ·
Last vector TG minutes + next vector TG meeting By Krste Asanovic ·
Thoughts for Vector TG Meeting Friday June 12 2 messages By David Horner ·
Vector Task Group minutes 2020/5/15 30 messages By Krste Asanovic ·
[RISC-V][tech-vector-ext] Intrinsics for vector programming in C. 16 messages By Kai Wang ·
Vector TG Meeting Friday May 29 By Krste Asanovic ·
Vector Task Group minutes 2020/5/15 - CLSTR for in-register to in-memory alignment By David Horner ·
Vector Task Group minutes 2020/5/15 - V0.8 design with SLEN=8 2 messages By David Horner ·
Vector Task Group minutes 2020/5/15 - precise layout not matter 2 messages By David Horner ·
MLEN=1 update 5 messages By Krste Asanovic ·
Vector TG group meeting tomorrow By Krste Asanovic ·
Vector extension TG meeting minutes 2020/5/1 6 messages By Krste Asanovic ·
spec updates and next meeting By Krste Asanovic ·
More thoughts on Git update (8a9fbce) Added fractional LMUL 16 messages By David Horner ·
Thoughts on Git update (8a9fbce) Added fractional LMUL, including modifying vector data register and vector mask register layouts for SLEN<VLEN implementations. 5 messages By David Horner ·
[riscv/riscv-v-spec] the differing nature of LMUL > 1 and fractional LMUL (#382) 3 messages By David Horner ·
make SEW be the largest element width 3 messages By Krste Asanovic ·
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