Date: 2020/8/21 Task Group: Vector Extension Chair: Krste Asanovic Co-Chair: Roger Espasa Number of Attendees: ~12 Current issues on github: https://github.com/riscv/riscv-v-spec Issues discussed: #50

Date: 2020/9/4 Task Group: Vector Extension Chair: Krste Asanovic Co-Chair: Roger Espasa Number of Attendees: ~20 Current issues on github: https://github.com/riscv/riscv-v-spec Issues discussed: Spec

Date: 2020/9/18 Task Group: Vector Extension Chair: Krste Asanovic Co-Chair: Roger Espasa Number of Attendees: ~17 Current issues on github: https://github.com/riscv/riscv-v-spec #551 Memory orderings

Hi team, Do we have a plan to write a V-extension white paper? Is there any interest? I'm thinking along the lines of ARM's SVE paper in IEEE Micro '17. I don't know if this is feasible or appropriate

From 0.9 stable spec, 5.3.1, table (no number), vector masking is referred to as having LSB. This suggests, yet does not require, that the mask field for each element is greater than bit-size 1. From

Krste

Date: 2020/9/25 Task Group: Vector Extension Chair: Krste Asanovic Co-Chair: Roger Espasa Number of Attendees: ~14 Current issues on github: https://github.com/riscv/riscv-v-spec Issues discussed #551

In the latest vector proposal (draft of version 1.0), there is the following restriction on widening instructions (section 11.2) For all widening instructions, the destination EEW and EMUL values must

Reminder we’ll be meeting tomorrow in usual slot. I’d like to spend the time discussing imprecise trap handling for embedded vector systems. Hopefully, we can all see the new correct link on Google Ca

Krste

Should vid.v raise an illegal instruction exception when masked and when the destination group overlaps v0 ? Should vid.v raise an illegal instruction exception when vstart > 0 ?

Vector Extension Task Group Meeting When: Friday, 12 June 2020 8:00am to 9:00am (UTC-07:00) America/Los Angeles Repeats: Weekly on Friday, through Thursday, 8 October 2020 Organizer: Krste Asanovic kr

Per calendar instructions, in usual time slot, Proposed agenda: #560 vmulh rounding mode #576 vlsegff exception behavior #550 names/contents of initial vector subsets #568 disabling/context swtiching

Date: 2020/10/2 Task Group: Vector Extension Chair: Krste Asanovic Co-Chair: Roger Espasa Number of Attendees: ~12 Current issues on github: https://github.com/riscv/riscv-v-spec Issues discussed; # I

Date: 2020/10/9 Task Group: Vector Extension Chair: Krste Asanovic Co-Chair: Roger Espasa Number of Attendees: ~12 Current issues on github: https://github.com/riscv/riscv-v-spec # 576 vlsegff excepti

Hi, what is a reasonable sequence to insert an element into an arbitrary position in the vector? I considered the following sequence (assume the input vector is v12) vid.v v1 vmseq.vx v0, v1, <index>

Date: 2020/10/16 Task Group: Vector Extension Chair: Krste Asanovic Co-Chair: Roger Espasa Number of Attendees: ~16 Current issues on github: https://github.com/riscv/riscv-v-spec # Definition of Done

Forwarding this to tech-vector-ext; couple comments below. Indeed, I've found other microarchitectural reasons to favor this approach (e.g., speculating through mask-register values). Enumerating all

Reminder: No meeting next Friday October 30. Date: 2020/10/23 Task Group: Vector Extension Chair: Krste Asanovic Co-Chair: Roger Espasa Number of Attendees: ~12 Current issues on github: https://githu

I'm working through updates to vector spec, and one part of clean up is changing text where it has mandatory raising of illegal instruction exceptions on unsupported encodings to instead state the enc