Date: 2020/10/2 Task Group: Vector Extension Chair: Krste Asanovic Co-Chair: Roger Espasa Number of Attendees: ~12 Current issues on github: https://github.com/riscv/riscv-v-spec Issues discussed; # I

Per calendar instructions, in usual time slot, Proposed agenda: #560 vmulh rounding mode #576 vlsegff exception behavior #550 names/contents of initial vector subsets #568 disabling/context swtiching

Vector Extension Task Group Meeting When: Friday, 12 June 2020 8:00am to 9:00am (UTC-07:00) America/Los Angeles Repeats: Weekly on Friday, through Thursday, 8 October 2020 Organizer: Krste Asanovic kr

Should vid.v raise an illegal instruction exception when masked and when the destination group overlaps v0 ? Should vid.v raise an illegal instruction exception when vstart > 0 ?

Krste

Reminder we’ll be meeting tomorrow in usual slot. I’d like to spend the time discussing imprecise trap handling for embedded vector systems. Hopefully, we can all see the new correct link on Google Ca

In the latest vector proposal (draft of version 1.0), there is the following restriction on widening instructions (section 11.2) For all widening instructions, the destination EEW and EMUL values must

Date: 2020/9/25 Task Group: Vector Extension Chair: Krste Asanovic Co-Chair: Roger Espasa Number of Attendees: ~14 Current issues on github: https://github.com/riscv/riscv-v-spec Issues discussed #551

Krste

From 0.9 stable spec, 5.3.1, table (no number), vector masking is referred to as having LSB. This suggests, yet does not require, that the mask field for each element is greater than bit-size 1. From

Hi team, Do we have a plan to write a V-extension white paper? Is there any interest? I'm thinking along the lines of ARM's SVE paper in IEEE Micro '17. I don't know if this is feasible or appropriate

Date: 2020/9/18 Task Group: Vector Extension Chair: Krste Asanovic Co-Chair: Roger Espasa Number of Attendees: ~17 Current issues on github: https://github.com/riscv/riscv-v-spec #551 Memory orderings

Date: 2020/9/4 Task Group: Vector Extension Chair: Krste Asanovic Co-Chair: Roger Espasa Number of Attendees: ~20 Current issues on github: https://github.com/riscv/riscv-v-spec Issues discussed: Spec

Date: 2020/8/21 Task Group: Vector Extension Chair: Krste Asanovic Co-Chair: Roger Espasa Number of Attendees: ~12 Current issues on github: https://github.com/riscv/riscv-v-spec Issues discussed: #50

Ahead of the vector meeting I would like to see if we can address or at least get direction on some of the flagged for pre-v1.0 resolution. There are 3 related flagged issues that all deal with vstart

I believe I added the correct zoom info on the correct new calendar for tomorrow’s vector task group meeting. Please check and advise if you’re not seeing it, Krste

i was made aware of this paper. risc-v vectors are mentioned. one of the key conclusions are (from the abstract) Our experiments show that VLA code reaches about 90% of the performance of vector lengt

Reminder there’s no vector TG meeting tomorrow (I have a conflict). We’ll be meeting again on Friday Sep 18 (I’ll work with Stephano to figure out new calendar scheme), Krste

what are the use cases? do we have examples in mind when they would/could be used? are there examples of what developers would want from previous efforts on vector machines? can we write them down? th

Though I don’t know if we’re affected by calendar changes, Krste