Signed v Unsigned Immediate: 4 messages By CDS ·
Decompress Instruction 3 messages By lidawei14@... ·
EEW and non-indexed loads/stores 2 messages By Roger Ferrer Ibanez ·
Cancelling Vector TG meeting today By Krste Asanovic ·
GNU toolchain with RVV intrinsic support 4 messages By Kito Cheng ·
V extension groups analogue to the standard groups 13 messages By tobias.strauch@... ·
[RISC-V] [tech-virt-mem] [RISC-V] [tech-vector-ext] Integer Overflow/Saturation Operations By Andy Glew Si5 ·
VFRECIP/VFRSQRT instructions 51 messages By andrew@... ·
Cancelled Event: Vector Extension Task Group Meeting - Friday, 14 August 2020 #cal-cancelled By Calendar ·
Cancelling vector TG meeting this week By Krste Asanovic ·
Integer Overflow/Saturation Operations 4 messages By CDS ·
Fixed Point (Chapter 13): Clarification Request 10 messages By CDS ·
Vector TG minutes for 2020/8/7 meeting By Krste Asanovic ·
Vector TG meeting minutes 2020/7/31 meeting By Krste Asanovic ·, used as negation 2 messages By CDS ·
[riscv/riscv-v-spec] For V1.0 - Make unsigned scalar integer in widening instructions 2 * SEW (#427) (and signed) 3 messages By David Horner ·
Proposed WG: RISC V needs CMOs, and hence a CMO Working Group By Andy Glew Si5 ·
Vector TG Minutes for 2020/7/24 meeting By Krste Asanovic ·
Issue #365 vsetvl{i} x0, x0 instruction forms 15 messages By Krste Asanovic ·
Duplicate Counting Instruction 6 messages By lidawei14@... ·