I added my proposal to github: https://github.com/riscv/riscv-v-spec/issues/425 appended below for those not following github Krste This proposal is a modification of earlier idea to add effective ele

There are two separate issues noted with the proposal to fixed-size vector load/stores. One is the additional vsetvli instructions needed, and the second is the additional widening instructions requir

Also a reminder that the next meeting will be a half hour earlier. Please check the group's calender for details. Krste Date: 2020/4/17 Task Group: Vector Extension Chair: Krste Asanovic Number of Att

Previous issues I opened on fractional LMUL were exploratory, suggesting various ways to encode and enable the feature. The latest 4 issues opened on github are specific proposals based on the strawma

Date: 2020/4/03 Task Group: Vector Extension Chair: Krste Asanovic Number of Attendees: ~15 Current issues on github: https://github.com/riscv/riscv-v-spec Issues discussed: #354/362 The following iss

Hi, all I have a problem about the usage of VectorAMO Operations. In the spec, there is only two sentences to describe the usageof Vector AMO Operations. Who have the concrete sample or other applicat

Hi, Nick That is a good suggestion for my code, thank you very much. But I develop my code depend on spec 0.7.1. The q-wide instructions had not been added to the spec. And I am confused with the upda

I agree with your point. But nowadays, the spec is not stable, and there is no target SOC to verify it. So, in my opinion, the number of instructions is an important indicator at present. 发件人: Bruce H

Hi Damon, Thanks for providing a concrete example! I think you can improve the performance of your first example (non-widening loads). Instead of immediately widening, you could instead perform your s

The number of instructions does not necessarily correspond to the speed, and especially not to the PPA or efficiency. Making the load/store simpler might save enough area to make it as or more energy

Hi，all I have some applications about byte/halfword/word vector load/stores, like gemm, direct convolution and son on. For 3x3 direct convolution, the code without byte/halfword/word vector load/store

We will be meeting again this morning. I hope to focus on closing on features for upcoming 0.9 release. Krste

I am developing sparse matrix codes using the vector extension on RISCV32 using SPIKE simulator. Based on my understanding of the spec thus far, I wanted to ask a couple of questions about the spec. I

I've been wading through the fractional LMUL discussion on github but believe the simple basic solution below meets the immediate needs, without blocking possible reuse of unused register fields later

This observation is a bit of a memory side issue but is tied to vector indexed loading semantics. The problem that I see is that my address offsets in the vector indexed load instruction are rather la

Date: 2020/3/20 Task Group: Vector Extension Chair: Krste Asanovic Number of Attendees: ~20 Current issues on github: https://github.com/riscv/riscv-v-spec Issues discussed: #367, #393 The following i

Maybe this has been stated already, and I just haven't seen it, but it seems like there's a constraint with fractional LMUL that wasn't there before. The compiler must ensure that: LMUL >= SEW/ELEN. I

I neglected to send an earlier reminder, but the vector TG meeting will be happening today per member calendar details, Krste

This is the fourth installation of the Simple Fractioanl LMUL design. It does not yet address SLEN and a suggestion for a fractional SLEN (fracSLEN). It should however clarify the ramifications of the

I am sending out the partial description of the next itteration for the Simple Fractioanl LMUL design. It is incomplete because I only recently clarified in my own mind a means to represent the concep