I'm cancelling meeting again, as I still have not been able to clean spec. I realize it will be more efficient for folks to wait for a clean version for a complete read through. Few issues are being r

I'm still working through spec cleanup. The list and github has been quiet, and I have no new issues to raise, so I suggest we cancel this meeting and push out for a week. Krste

Date: 2021/02/19 Task Group: Vector Extension Chair: Krste Asanovic Vice-Chair: Roger Espasa Number of Attendees: ~23 Current issues on github: https://github.com/riscv/riscv-v-spec # Next Meeting/Fre

Hi everyone, I’ve updated the Zfinx spec to show which V-extension instructions are affected. https://github.com/riscv/riscv-zfinx/blob/master/Zfinx_spec.adoc#vector Please review the list, and tell m

We’ll meet today in usual slot, details on Google calendar Agenda is to discuss any issues found while reading over the v0.10 spec. List and GitHub has been quite quiet, so this might be a short meeti

Date: 2020/12/18 Task Group: Vector Extension Chair: Krste Asanovic Co-Chair: Roger Espasa Number of Attendees: ~10 Current issues on github: https://github.com/riscv/riscv-v-spec Note: No more meetin

Hello, I've just joined the RISC-V technical community and the V Extension Task group. I have very substantial experience in careful technical documentation (I wrote the RFCs for gzip and DEFLATE, and

Date: 2021/02/05 Task Group: Vector Extension Chair: Krste Asanovic Vice-Chair: Roger Espasa Number of Attendees: ~16 Current issues on github: https://github.com/riscv/riscv-v-spec # Next Meeting It

We’ll meet tomorrow in usual slot per TG calendar. The agenda is to review any feedback on the 0.10 spec and then to proceed through any outstanding issues, Krste

Hi all, As part of the (first) annual process of holding elections for chairs of current Task Groups, this is a request for candidates for the chair and vice-chair positions in the Vector Extension ta

Date: 2021/01/29 Task Group: Vector Extension Chair: Krste Asanovic Co-Chair: Roger Espasa Number of Attendees: ~16 Current issues on github: https://github.com/riscv/riscv-v-spec # Meetings Meetings

I cut a v0.10 release after adding all the substantial pending updates. There is still a bunch of work to do before public review, but this is a convenient milestone for toolchain developers, Krste

I scheduled next vector TG meeting tomorrow in usual slot with usual zoom link on TG Google calendar. I hope to push out updated spec sometime before then, Krste

I was going to restart the vector TG meetings next week (Jan 29), and have a goal of having most pending updates added to the spec a few days before then. Krste

I see it on riscv-v-spec commit: 0e8cdeb26bb98de2b1089d79a681af2c5a65e712 vmv.x.s rd, vs2 # x[rd] = vs2[0] (rs1=0) vmv.x.s belong to VWXUNARY0 and OPMVV But OPMVV has only vs1 no rs1, see : funct6 | v

I don’t see Vector Extension meetings on the calendar. Is the group meeting? Bill Bill Huffman Distinguished Engineer T: 408.944.7613

Agenda is hopefully clearing up any remaining major issues before 1.0 draft can go out, Krste

Date: 2020/12/04 Task Group: Vector Extension Chair: Krste Asanovic Co-Chair: Roger Espasa Number of Attendees: ~12 Current issues on github: https://github.com/riscv/riscv-v-spec Note: No meeting wee

Hi，David Can we see the git of your work? My code has not been upload to git, and I will show it in the mail. Does this mean the 32 vector registers are not enough, or that the number of elements for

Hi，all Recently, I optimized the kernel of GEMM for int8 data. I found that there was no good solution to do in by the use of the present vector ISA. The mainly difficult I meet is: The accumulator is