Tech: Zfinx Task Group tech-zfinx@lists.riscv.org

Charter

The Zfinx task group will specify how to share the integer (X) registers with the floating point (F) registers, specifically to save silicon area. The group will specify the requirements for the ISA, ABI and the toolchain. The charter covers RV32 and RV64 implementations with D (64-bit), F (32-bit) and H (16-bit) floating point registers. RV128 and Q(128-bit) are considered out of scope, but should be resolvable as a simple extension to the final specification.

 Deliverables

1.     A complete specification of Zfinx for inclusion in the RISC-V ISA manual

Roadmap

1.     Completely specify F-in-X (RV32F with Zfinx) and D-in-X (RV64D with Zfinx)

2.     Extend to RV64F, RV64H, RV32H i.e. cases where XLEN > FLEN

3.     Extend to RV32D, the only supported case where XLEN < FLEN

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