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Tech: Zfinx Task Group tech-zfinx-archive-2022@lists.riscv.org
Charter
The Zfinx task group will specify how to share the integer (X) registers with the floating point (F) registers, to save silicon area and to free up encoding space. The group will specify the requirements for the ISA and the toolchain. The charter covers RV32 and RV64 implementations with D (64-bit), F (32-bit) and Zfh (16-bit) floating point registers. RV128 and Q(128-bit) are considered out of scope, but should be resolvable as a simple extension to the final specification.
Deliverables
1. A complete specification of Zfinx for inclusion in the RISC-V ISA manual
Roadmap
1. Completely specify RV32F Zfinx, RV32FD Zfinx
2. Extend to RV32D where XLEN < FLEN
3. Deliver SAIL model, QEMU model
4. Pass architectural tests
5. Delivery of GCC and GDB
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