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Zfinx status
Hi everyone, Here is the latest status of the Zfinx extension 1. Spec updates a. The configurations have changed so it’s no longer F + Zfinx, now it’s Z[FDQ]inx b. Jiawei – I think this affects the to
Hi everyone, Here is the latest status of the Zfinx extension 1. Spec updates a. The configurations have changed so it’s no longer F + Zfinx, now it’s Z[FDQ]inx b. Jiawei – I think this affects the to
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By Tariq Kurd
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Zfinx behaviour when misa.mxl is programmed smaller than XLEN 3 messages
Hi everyone, https://github.com/riscv/riscv-zfinx/issues/10 The question is how to handle the cases where misa.mxl is programmed so that XLEN is smaller than the maximum XLEN. It seems sensible that e
Hi everyone, https://github.com/riscv/riscv-zfinx/issues/10 The question is how to handle the cases where misa.mxl is programmed so that XLEN is smaller than the maximum XLEN. It seems sensible that e
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By Tariq Kurd
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LLVM upstream developer query about Zfinx 2 messages
https://github.com/riscv/riscv-zfinx/issues/8 Can anyone who understand the implementation of Zfinx in either GCC or LLVM help resolve this issue on github please? Thanks! Tariq Tariq Kurd Processor D
https://github.com/riscv/riscv-zfinx/issues/8 Can anyone who understand the implementation of Zfinx in either GCC or LLVM help resolve this issue on github please? Thanks! Tariq Tariq Kurd Processor D
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By Tariq Kurd
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register pair handling in RV32D 2 messages
Hi everyone, Following John Hauser’s advice I’ve removed big endian register swapping for Zfinx in RV32D. This a spec change for big-endian mode. Weiwu/Jiawei – RV32D will need to change (I’m sorry! 实
Hi everyone, Following John Hauser’s advice I’ve removed big endian register swapping for Zfinx in RV32D. This a spec change for big-endian mode. Weiwu/Jiawei – RV32D will need to change (I’m sorry! 实
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By Tariq Kurd
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Request for Candidates for Zfinx Extension Task Group Chair and Vice-Chair
Hi all, As part of the (first) annual process of holding elections for chairs of current Task Groups, this is a request for candidates for the chair and vice-chair positions in the Zfinx Extension tas
Hi all, As part of the (first) annual process of holding elections for chairs of current Task Groups, this is a request for candidates for the chair and vice-chair positions in the Zfinx Extension tas
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By Chuanhua Chang
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Zfinx DoD checklist 13 messages
Hi everyone, https://docs.google.com/spreadsheets/d/1B_837wZStMzX-Ggn9fVQgDMnnQGV2kXC/edit#gid=111592862 I’ve rebased the Zfinx status spreadsheet on the latest version. I have quite a few rows I’m no
Hi everyone, https://docs.google.com/spreadsheets/d/1B_837wZStMzX-Ggn9fVQgDMnnQGV2kXC/edit#gid=111592862 I’ve rebased the Zfinx status spreadsheet on the latest version. I have quite a few rows I’m no
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By Tariq Kurd
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Zfinx SAIL support issues
Hi everyone, We are completely stuck on SAIL, there have been no email responses about technical queries and the pull requests have not been reviewed. https://github.com/rems-project/sail-riscv/pull/7
Hi everyone, We are completely stuck on SAIL, there have been no email responses about technical queries and the pull requests have not been reviewed. https://github.com/rems-project/sail-riscv/pull/7
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By Tariq Kurd
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ZFINX/ SAIL status and issues
Hi everyone, This is our SAIL status for Zfinx. Ibrahim is stuck on many issues, most of which are on github and unresolved. Prasanth helped for a while (just 1-day a week so painfully slowly) but now
Hi everyone, This is our SAIL status for Zfinx. Ibrahim is stuck on many issues, most of which are on github and unresolved. Prasanth helped for a while (just 1-day a week so painfully slowly) but now
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By Tariq Kurd
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Regs access when XLEN<FLEN with F-extension 3 messages
Hello everyone, Is that the specified register could access old regs or only even regs for F-extension. The Zfinx_spec give the D-extension result and I am not sure the case in F-extension. Thank you,
Hello everyone, Is that the specified register could access old regs or only even regs for F-extension. The Zfinx_spec give the D-extension result and I am not sure the case in F-extension. Thank you,
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By jiawei
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SAIL updates for Zfinx 8 messages
Hi Peter, We work in Huawei in Bristol, and I’m the chair of the Zfinx RISC-V task group. My colleague Ibrahim has been updating SAIL to implement Zfinx (sharing floating point and integer register fi
Hi Peter, We work in Huawei in Bristol, and I’m the chair of the Zfinx RISC-V task group. My colleague Ibrahim has been updating SAIL to implement Zfinx (sharing floating point and integer register fi
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By Tariq Kurd
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Brief notes from call with Neel Gala / IIT madras
We discussed FP testing - It’s on IIT Madras’s list, but won’t be tackled soon - Ibrahim will look at importing the IBM test suite into test-float, and comparing the expected results against the IBM r
We discussed FP testing - It’s on IIT Madras’s list, but won’t be tackled soon - Ibrahim will look at importing the IBM test suite into test-float, and comparing the expected results against the IBM r
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By Tariq Kurd
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FP testing status and Zfinx 3 messages
We had a discussion with Allen Baum about testing the SAIL model edits for Zfinx. Allen suggests we use the CTG test generator from Incore, for base ISA architectural tests and has a coverage model fo
We had a discussion with Allen Baum about testing the SAIL model edits for Zfinx. Allen suggests we use the CTG test generator from Incore, for base ISA architectural tests and has a coverage model fo
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By Tariq Kurd
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SAIL model and architectural tests 3 messages
Hi Allen, Do you have some time to discuss the SAIL model and architectural tests with us later this week? Maybe we can have a call Thursday/Friday. I have the toolchain/runtimes meeting at 9am/5pm Th
Hi Allen, Do you have some time to discuss the SAIL model and architectural tests with us later this week? Maybe we can have a call Thursday/Friday. I have the toolchain/runtimes meeting at 9am/5pm Th
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By Tariq Kurd
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clarification required for nan boxing and RV64F 6 messages
Hi everyone, In the Zfinx spec we decided to delete all floating point load/stores, because the integer load/stores are sufficient, and to free up encoding space. NaN-boxing can be done in software by
Hi everyone, In the Zfinx spec we decided to delete all floating point load/stores, because the integer load/stores are sufficient, and to free up encoding space. NaN-boxing can be done in software by
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By Tariq Kurd
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Zfinx - getting to done 2 messages
Hi Allen, Yes – compliance / architectural tests, and some help with them would be great. Can we have a chat about this next week with Mark Hill as well? Maybe straight after the code size reduction m
Hi Allen, Yes – compliance / architectural tests, and some help with them would be great. Can we have a chat about this next week with Mark Hill as well? Maybe straight after the code size reduction m
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By Tariq Kurd
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Zfinx status and Fp tests 4 messages
Hi everyone, I’m out of the office for 10 days from tomorrow, and I haven’t sent a status for a while. Here’s where we are up to: 1. My colleague Mark Hill has implemented RV32F Zfinx in SAIL a. There
Hi everyone, I’m out of the office for 10 days from tomorrow, and I haven’t sent a status for a while. Here’s where we are up to: 1. My colleague Mark Hill has implemented RV32F Zfinx in SAIL a. There
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By Tariq Kurd
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FP test suite(s) 11 messages
IBM has done a great deal of work on testing FP. Here are some excellent pointers: https://www.research.ibm.com/haifa/projects/verification/fpgen/papers/ieee-test-suite-v2.pdf https://researcher.watso
IBM has done a great deal of work on testing FP. Here are some excellent pointers: https://www.research.ibm.com/haifa/projects/verification/fpgen/papers/ieee-test-suite-v2.pdf https://researcher.watso
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By Allen Baum
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Getting started with Zfinx compliance tests 3 messages
HI Allen, To understand how to get started with adding compliance tests, I’ve looked at github: https://github.com/riscv/riscv-compliance Which implies I need a toolchain and OVPSim to run them. I gue
HI Allen, To understand how to get started with adding compliance tests, I’ve looked at github: https://github.com/riscv/riscv-compliance Which implies I need a toolchain and OVPSim to run them. I gue
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By Tariq Kurd
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REcorporate asignment 2 messages
Hi Jim. >But I don't see a Huawei copyright assignment for binutils which is a problem. What problem does this cause? Does it prevent testing in the short term, or is it related to merging our changes
Hi Jim. >But I don't see a Huawei copyright assignment for binutils which is a problem. What problem does this cause? Does it prevent testing in the short term, or is it related to merging our changes
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By Tariq Kurd
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Zfinx status and remaining tasks 14 messages
Hi Mark, Here’s where we are up to: Spec: done, pending testing GCC: done for all configurations (by Yu Chao), but Huawei doesn’t have a corporate assignment in place for binutils (only for gcc and li
Hi Mark, Here’s where we are up to: Spec: done, pending testing GCC: done for all configurations (by Yu Chao), but Huawei doesn’t have a corporate assignment in place for binutils (only for gcc and li
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By Tariq Kurd
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