Congratulations to Tariq and all the people who helped produce this on the zfinx TG and in the riscv organization. As everyone knows this is the first of many crucial extensions to provide a more comp

All, After a discussion with Tariq, we agreed that adding the Creative Commons License with Attribution (CC-BY-4.0) text in a LICENSE file was a good idea. This is the same license which has been on t

Hi everyone, Here is the latest status of the Zfinx extension 1. Spec updates a. The configurations have changed so it’s no longer F + Zfinx, now it’s Z[FDQ]inx b. Jiawei – I think this affects the to

Hi Jiawei, Do you have an updated status on the Zfinx toolchain and Qemu / Spike development? Thanks! Tariq Tariq Kurd Processor Design I RISC-V Cores, Bristol E-mail: Tariq.Kurd@... Company: Huawei t

Hi everyone, https://github.com/riscv/riscv-zfinx/issues/10 The question is how to handle the cases where misa.mxl is programmed so that XLEN is smaller than the maximum XLEN. It seems sensible that e

https://github.com/riscv/riscv-zfinx/issues/8 Can anyone who understand the implementation of Zfinx in either GCC or LLVM help resolve this issue on github please? Thanks! Tariq Tariq Kurd Processor D

Hi everyone, Following John Hauser’s advice I’ve removed big endian register swapping for Zfinx in RV32D. This a spec change for big-endian mode. Weiwu/Jiawei – RV32D will need to change (I’m sorry! 实

Hi all, As part of the (first) annual process of holding elections for chairs of current Task Groups, this is a request for candidates for the chair and vice-chair positions in the Zfinx Extension tas

Hi everyone, https://docs.google.com/spreadsheets/d/1B_837wZStMzX-Ggn9fVQgDMnnQGV2kXC/edit#gid=111592862 I’ve rebased the Zfinx status spreadsheet on the latest version. I have quite a few rows I’m no

Hi everyone, We are completely stuck on SAIL, there have been no email responses about technical queries and the pull requests have not been reviewed. https://github.com/rems-project/sail-riscv/pull/7

Hi everyone, This is our SAIL status for Zfinx. Ibrahim is stuck on many issues, most of which are on github and unresolved. Prasanth helped for a while (just 1-day a week so painfully slowly) but now

Hello everyone， Is that the specified register could access old regs or only even regs for F-extension. The Zfinx_spec give the D-extension result and I am not sure the case in F-extension. Thank you,

Hi Peter, We work in Huawei in Bristol, and I’m the chair of the Zfinx RISC-V task group. My colleague Ibrahim has been updating SAIL to implement Zfinx (sharing floating point and integer register fi

We discussed FP testing - It’s on IIT Madras’s list, but won’t be tackled soon - Ibrahim will look at importing the IBM test suite into test-float, and comparing the expected results against the IBM r

We had a discussion with Allen Baum about testing the SAIL model edits for Zfinx. Allen suggests we use the CTG test generator from Incore, for base ISA architectural tests and has a coverage model fo

Hi Allen, Do you have some time to discuss the SAIL model and architectural tests with us later this week? Maybe we can have a call Thursday/Friday. I have the toolchain/runtimes meeting at 9am/5pm Th

Hi everyone, In the Zfinx spec we decided to delete all floating point load/stores, because the integer load/stores are sufficient, and to free up encoding space. NaN-boxing can be done in software by

Hi Allen, Yes – compliance / architectural tests, and some help with them would be great. Can we have a chat about this next week with Mark Hill as well? Maybe straight after the code size reduction m

Hi everyone, I’m out of the office for 10 days from tomorrow, and I haven’t sent a status for a while. Here’s where we are up to: 1. My colleague Mark Hill has implemented RV32F Zfinx in SAIL a. There

IBM has done a great deal of work on testing FP. Here are some excellent pointers: https://www.research.ibm.com/haifa/projects/verification/fpgen/papers/ieee-test-suite-v2.pdf https://researcher.watso